{"id":320,"date":"2015-12-27T23:25:24","date_gmt":"2015-12-27T22:25:24","guid":{"rendered":"http:\/\/www.igatamus.com\/bgc\/?p=320"},"modified":"2017-10-06T23:26:09","modified_gmt":"2017-10-06T21:26:09","slug":"acces-aux-parametres-internes-du-nom-m340","status":"publish","type":"post","link":"https:\/\/www.igatamus.com\/bgc\/2015\/12\/27\/acces-aux-parametres-internes-du-nom-m340\/","title":{"rendered":"Acc\u00e8s aux param\u00e8tres internes du NOM M340"},"content":{"rendered":"

Exemple de code:
\nif dataCh010Get then
\nread_var(addm(‘0.1.0’), ‘%MW’, dataCh010StartAddr, dataCh010Size, dataCh010Mgt, dataCh010Buff);
\ndataCh010Get := false;
\nend_if;<\/p>\n

Contenu de la zone:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Address<\/td>\nField kind<\/td>\nDesignation<\/td>\n<\/tr>\n
%MW0<\/td>\nINT<\/td>\nTx Start Delay: wait a delay before sending data. It is commonly used with the half duplex modem mode to set the RTS signal, wait the CTS signal and then wait this delay before sending data. It seems to conform to FOCKS mechanism.<\/td>\n<\/tr>\n
%MW1<\/td>\nINT<\/td>\nTx End delay: wait a while after the last byte sent. It is commonly used with half duplex modem mode to maintain the RTS signal this time, to let enougth time to the modem to send the buffer to the peer, before switching to reception mode. It seems to conform to the FOCKS mechanism.<\/td>\n<\/tr>\n
%MW16<\/td>\nINT<\/td>\nbus_message_count<\/td>\n<\/tr>\n
%MW18<\/td>\nINT<\/td>\nbus_com_error_count<\/td>\n<\/tr>\n
%MW20<\/td>\nINT<\/td>\nbus_except_error_count<\/td>\n<\/tr>\n
%MW22<\/td>\nINT<\/td>\nslave_mes_count<\/td>\n<\/tr>\n
%MW24<\/td>\nINT<\/td>\nslave_no_resp_count<\/u><\/td>\n<\/tr>\n
%MW26<\/td>\nINT<\/td>\nslave_NAK_count<\/td>\n<\/tr>\n
%MW28<\/td>\nINT<\/td>\nslave_busy_count<\/u><\/td>\n<\/tr>\n
%MW30<\/td>\nINT<\/td>\nbus_char_overrun_count<\/u><\/td>\n<\/tr>\n
%MW30<\/td>\nINT<\/td>\nInternal\u00a0com_event_count<\/td>\n<\/tr>\n
%MW30<\/td>\nINT<\/td>\nInternal\u00a0diag_register<\/u><\/td>\n<\/tr>\n
%MW30<\/td>\nINT<\/td>\nInternal\u00a0successfull_mstr_count<\/td>\n<\/tr>\n
%MW30<\/td>\nINT<\/td>\nInternal\u00a0successfull_slave_count<\/td>\n<\/tr>\n
%MW40<\/td>\nINT<\/td>\nInternal\u00a0bad_adr_count<\/u><\/td>\n<\/tr>\n
%MW42<\/td>\nINT<\/td>\nInternal\u00a0bad_length_count<\/u><\/td>\n<\/tr>\n
%MW44<\/td>\nINT<\/td>\nInternal\u00a0mstr_retry_count<\/u><\/td>\n<\/tr>\n
%MW46<\/td>\nINT<\/td>\nInternal\u00a0STOP_BYTES<\/td>\n<\/tr>\n
%MW48<\/td>\nINT<\/td>\nInternal\u00a0listenOnlyMode<\/u><\/td>\n<\/tr>\n
%MW50<\/td>\nINT<\/td>\nInternal KindOfFlowControl (0:full duplex, 1 RTS, 2 DTR)<\/td>\n<\/tr>\n
%MW100<\/td>\nINT<\/td>\nInternal conf mode<\/td>\n<\/tr>\n
%MD102<\/td>\nDINT<\/td>\nInternal conf baudrate<\/td>\n<\/tr>\n
%MW104<\/td>\nINT<\/td>\nInternal conf dataLength<\/td>\n<\/tr>\n
%MW106<\/td>\nINT<\/td>\nInternal conf parity<\/td>\n<\/tr>\n
%MW108<\/td>\nINT<\/td>\nInternal conf stopBitNb<\/td>\n<\/tr>\n
%MW110<\/td>\nINT<\/td>\nInternal conf rs232<\/td>\n<\/tr>\n
%MW112<\/td>\nINT<\/td>\nInternal conf hwFlowCtrl<\/td>\n<\/tr>\n
%MW114<\/td>\nINT<\/td>\nInternal conf modemMode<\/td>\n<\/tr>\n
%MW116<\/td>\nINT<\/td>\nInternal conf framesDelay<\/td>\n<\/tr>\n
%MW118<\/td>\nINT<\/td>\nInternal conf silence<\/td>\n<\/tr>\n
%MW120<\/td>\nINT<\/td>\nInternal conf slaveAnswerDelay<\/td>\n<\/tr>\n
%MW122<\/td>\nINT<\/td>\nInternal conf slaveNumber<\/td>\n<\/tr>\n
%MW124<\/td>\nINT<\/td>\nInternal conf slaveNumberExternal<\/td>\n<\/tr>\n
%MW126<\/td>\nINT<\/td>\nInternal conf polarizationModbus<\/td>\n<\/tr>\n
%MW128<\/td>\nINT<\/td>\nInternal conf polarizationUnitelway<\/td>\n<\/tr>\n
%MW130<\/td>\nINT<\/td>\nInternal conf nbRetries<\/td>\n<\/tr>\n
%MW132<\/td>\nINT<\/td>\nInternal conf rtsCtsTimeout<\/td>\n<\/tr>\n
%MW134<\/td>\nINT<\/td>\nInternal conf endOfFrameChar1<\/td>\n<\/tr>\n
%MW136<\/td>\nINT<\/td>\nInternal conf endOfFrameIncludedChar1<\/td>\n<\/tr>\n
%MW138<\/td>\nINT<\/td>\nInternal conf endOfFrameByteChar1<\/td>\n<\/tr>\n
%MW140<\/td>\nINT<\/td>\nInternal conf endOfFrameChar2<\/td>\n<\/tr>\n
%MW142<\/td>\nINT<\/td>\nInternal conf endOfFrameChar2<\/td>\n<\/tr>\n
%MW144<\/td>\nINT<\/td>\nInternal conf endOfFrameIncludedChar2<\/td>\n<\/tr>\n
%MW146<\/td>\nINT<\/td>\nInternal conf endOfFrameByteChar2<\/td>\n<\/tr>\n
%MW148<\/td>\nINT<\/td>\nInternal conf blindTimeMs<\/td>\n<\/tr>\n
%MW150<\/td>\nINT<\/td>\nInternal usePatchedTimings<\/td>\n<\/tr>\n
%MW152<\/td>\nINT<\/td>\nInternal t3_5ch<\/td>\n<\/tr>\n
%MW154<\/td>\nINT<\/td>\nInternal t1_5ch<\/td>\n<\/tr>\n
%MW156<\/td>\nINT<\/td>\nInternal tDelay<\/td>\n<\/tr>\n
%MD158<\/td>\nDINT<\/td>\nInternal conf KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW160<\/td>\nINT<\/td>\nInternal conf ctsDelayBeforeTx\u00a0<\/u>: In half duplex mode, on sending, the RTS signal raise, then when the CTS raise the delay is executed beforte sending the frame.<\/td>\n<\/tr>\n
%MW162<\/td>\nINT<\/td>\nInternal conf rtsDelayAfterTx<\/u>: In half duplex mode, after sending, the RTS signal is maintain until the delay is over.<\/td>\n<\/tr>\n
%MW200<\/td>\nINT<\/td>\nCurrent version of the local channel server (00.01)<\/td>\n<\/tr>\n
%MW201<\/td>\nINT<\/td>\nFlash Slave Address<\/td>\n<\/tr>\n
%MW202<\/td>\nINT<\/td>\nIs it authorized to change the address ?<\/td>\n<\/tr>\n
%MW1000<\/td>\nINT<\/td>\nModbus RTU Master: internal protocol code<\/td>\n<\/tr>\n
%MW1002<\/td>\nINT<\/td>\nModbus RTU Master: KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW1010<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0T1_5crS<\/td>\n<\/tr>\n
%MW1012<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0T1_5crR<\/td>\n<\/tr>\n
%MW1014<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0T3_5crS<\/td>\n<\/tr>\n
%MW1016<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0T3_5crR<\/td>\n<\/tr>\n
%MW1018<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0DelayInBits<\/u><\/td>\n<\/tr>\n
%MW1090<\/td>\nINT<\/td>\nModbus RTU Master: nb retries configured<\/td>\n<\/tr>\n
%MW1100<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0SlaveAnswerDelay10ms Broadcast<\/td>\n<\/tr>\n
%MW1101<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0SlaveAnswerDelay10ms Slave 1<\/td>\n<\/tr>\n
%MW1102<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0SlaveAnswerDelay10ms Slave 2<\/td>\n<\/tr>\n
%MW1103<\/td>\nINT<\/td>\n\u2026<\/td>\n<\/tr>\n
%MW1347<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0SlaveAnswerDelay10ms Slave 247<\/td>\n<\/tr>\n
%MW1348<\/td>\nINT<\/td>\nModbus RTU Master:\u00a0SlaveAnswerDelay10ms Point to Point<\/td>\n<\/tr>\n
%MW1500<\/td>\nINT<\/td>\nModbus RTU Slave: internal protocol code<\/td>\n<\/tr>\n
%MW1502<\/td>\nINT<\/td>\nModbus RTU Slave: KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW1510<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0T1_5crS<\/td>\n<\/tr>\n
%MW1512<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0T1_5crR<\/td>\n<\/tr>\n
%MW1514<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0T3_5crS<\/td>\n<\/tr>\n
%MW1516<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0T3_5crR<\/td>\n<\/tr>\n
%MW1518<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0DelayInBits<\/u><\/td>\n<\/tr>\n
%MW1600<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0SlaveAddr<\/td>\n<\/tr>\n
%MW1602<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0BlindTimeAfterReception<\/td>\n<\/tr>\n
%MW1604<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0blindTimeActivated<\/td>\n<\/tr>\n
%MW1606<\/td>\nINT<\/td>\nModbus RTU Slave:\u00a0ListenOnlyMode<\/td>\n<\/tr>\n
%MW2000<\/td>\nINT<\/td>\nModbus ASCII Master : internal protocol code<\/td>\n<\/tr>\n
%MW2002<\/td>\nINT<\/td>\nModbus ASCII Master : KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW2010<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0T1_5crS<\/td>\n<\/tr>\n
%MW2012<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0T1_5crR<\/td>\n<\/tr>\n
%MW2014<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0T3_5crS<\/td>\n<\/tr>\n
%MW2016<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0T3_5crR<\/td>\n<\/tr>\n
%MW2018<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0DelayInBits<\/u><\/td>\n<\/tr>\n
%MW2090<\/td>\nINT<\/td>\nModbus ASCII Master: nb retries configured<\/td>\n<\/tr>\n
%MW2100<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0SlaveAnswerDelay10ms Broadcast<\/td>\n<\/tr>\n
%MW2101<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0SlaveAnswerDelay10ms Slave 1<\/td>\n<\/tr>\n
%MW2102<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0SlaveAnswerDelay10ms Slave 2<\/td>\n<\/tr>\n
%MW2103<\/td>\nINT<\/td>\n\u2026<\/td>\n<\/tr>\n
%MW2347<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0SlaveAnswerDelay10ms Slave 247<\/td>\n<\/tr>\n
%MW2348<\/td>\nINT<\/td>\nModbus ASCII Master:\u00a0SlaveAnswerDelay10ms Point to Point<\/td>\n<\/tr>\n
%MW2500<\/td>\nINT<\/td>\nModbus ASCII Slave: internal protocol code<\/td>\n<\/tr>\n
%MW2502<\/td>\nINT<\/td>\nModbus ASCII Slave: KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW2510<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0T1_5crS<\/td>\n<\/tr>\n
%MW2512<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0T1_5crR<\/td>\n<\/tr>\n
%MW2514<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0T3_5crS<\/td>\n<\/tr>\n
%MW2516<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0T3_5crR<\/td>\n<\/tr>\n
%MW2518<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0DelayInBits<\/u><\/td>\n<\/tr>\n
%MW2600<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0SlaveAddr<\/td>\n<\/tr>\n
%MW2602<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0BlindTimeAfterReception<\/td>\n<\/tr>\n
%MW2604<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0blindTimeActivated<\/td>\n<\/tr>\n
%MW2606<\/td>\nINT<\/td>\nModbus ASCII Slave:\u00a0ListenOnlyMode<\/td>\n<\/tr>\n
%MW3000<\/td>\nINT<\/td>\nChar Mode: internal protocol code<\/td>\n<\/tr>\n
%MW3002<\/td>\nINT<\/td>\nChar Mode: KindOfFlowControl (0: none, 1: RTS automatic, 2: DTR automatic instead of RTS)<\/td>\n<\/tr>\n
%MW3100<\/td>\nINT<\/td>\nChar Mode:\u00a0Stop criteria present<\/td>\n<\/tr>\n
%MW3102<\/td>\nINT<\/td>\nChar Mode: Ticr<\/td>\n<\/tr>\n
%MW3104<\/td>\nINT<\/td>\nChar Mode: \u00a0EOF byte 1<\/td>\n<\/tr>\n
%MW3104<\/td>\nINT<\/td>\nChar Mode: \u00a0EOF char 1 added<\/td>\n<\/tr>\n
%MW3104<\/td>\nINT<\/td>\nChar Mode: \u00a0EOFbyte 2<\/td>\n<\/tr>\n
%MW3104<\/td>\nINT<\/td>\nChar Mode: \u00a0EOF char 2 added<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Exemple de code: if dataCh010Get then read_var(addm(‘0.1.0’), ‘%MW’, dataCh010StartAddr, dataCh010Size, dataCh010Mgt, dataCh010Buff); dataCh010Get := false; end_if; Contenu de la zone: Address Field kind Designation %MW0 INT Tx Start Delay: wait a delay before sending data. It is commonly used with the half duplex modem mode to set the RTS signal, wait the CTS signal and … <\/p>\n

Continuer la lecture de « Acc\u00e8s aux param\u00e8tres internes du NOM M340 »<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[4],"tags":[],"_links":{"self":[{"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/posts\/320"}],"collection":[{"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/comments?post=320"}],"version-history":[{"count":1,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/posts\/320\/revisions"}],"predecessor-version":[{"id":321,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/posts\/320\/revisions\/321"}],"wp:attachment":[{"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/media?parent=320"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/categories?post=320"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.igatamus.com\/bgc\/wp-json\/wp\/v2\/tags?post=320"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}