General

The internal processing time for inputs and outputs is the sum of the following:

  • MAST task system overhead time

  • maximum communication system reception time and input management time for implicit inputs/outputs

  • maximum communication system transmission time and output management time for implicit inputs/outputs

MAST Task System Overhead Time

For BMEP58•0•0 processors, the MAST task system overhead time is 700 μs.

NOTE: Three system words give information on the MAST task system overhead times:

  • %SW27: last cycle overhead time

  • %SW28: longest overhead time

  • %SW29: shortest overhead time

Implicit Input/Output Management Time

The implicit input management time is the sum of the following:

  • Fixed base of 25 μs

  • Sum of the input management times for each module (in the following table, IN)

The implicit output management time is the sum of the following:

  • Fixed base of 25 μs (FAST), 73 μs (MAST)

  • Sum of the output management times for each module (in the following table, OUT)

The table below shows the input (IN) and output (OUT) topological (T) and DDT (DDT) management times for each module.

Module

Input Management Time (IN) (μs)

Output Management Time (OUT) (μs)

Total Management Time (IN+OUT) (μs)

BMXDDI1602, 16 discrete inputs module

T:

60

40

100

DDT:

30

29

60

BMXDDI3202K, 32 discrete inputs module

T:

67

44

111

DDT:

34

31

64

BMXDDI6402K, 64 discrete inputs module

T:

87

63

150

DDT:

40

43

83

BMXDDO1602, 16 discrete outputs module

T:

60

45

105

DDT:

31

34

64

BMXDDO1612, 16 discrete outputs module

T:

60

45

105

DDT:

30

33

63

BMXDDO3202
BMXDDO3202H

T:

DDT:

BMXDDO3202K, 32 discrete outputs module

T:

67

51

118

DDT:

33

35

69

BMXDDO6402K, 64 discrete outputs module

T:

87

75

162

DDT:

40

50

89

BMXDDM16022, 8 discrete inputs and 8 discrete outputs module

T:

68

59

127

DDT:

44

51

95

BMXDDM3202K, 16 discrete inputs and 16 discrete outputs module

T:

75

63

138

DDT:

48

54

102

BMXDDM16025, 8 discrete inputs and 8 discrete outputs module

T:

68

59

127

DDT:

44

51

95

BMXDAI0805, 8 discrete inputs module

T:

60

40

100

DDT:

28

28

56

BMXDAI1602, 16 discrete inputs module

T:

60

40

100

DDT:

29

29

59

BMXDAI1603, 16 discrete inputs module

T:

60

40

100

DDT:

30

29

59

BMXDAI1604, 16 discrete inputs module

T:

60

40

100

DDT:

30

29

58

BMXDAO1605, 16 discrete outputs module

T:

60

45

105

DDT:

30

33

64

BMXAMI0410 analog module

T:

103

69

172

DDT:

43

42

85

BMXAMI0800 analog module

T:

103

69

172

DDT:

63

65

129

BMXAMI0810 analog module

T:

103

69

172

DDT:

63

65

128

BMXAMO0210 analog module

T:

65

47

112

DDT:

30

35

65

BMXAMO802 analog module

T:

110

110

220

DDT:

47

74

121

BMXAMM0600 analog module

T:

115

88

203

DDT:

82

80

162

BMXDRA0804, 8 discrete outputs module

T:

56

43

99

DDT:

27

31

58

BMXDRA0805, 8 discrete outputs module

T:

56

43

99

DDT:

28

31

59

BMXEHC0200 dual-channel counting module

T:

102

93

195

DDT:

101

108

208

BMXEHC0800 eight-channel counting module

T:

228

282

510

DDT:

261

317

578

Communication System Time

Communication (excluding telegrams) is managed during the MAST task internal processing phases:

  • on input for receiving messages

  • on output for sending messages

The MAST task cycle time is, therefore, affected by the communication traffic. The communication time spent per cycle varies considerably, based on the following elements:

  • traffic generated by the processor: number of communication EFs active simultaneously

  • traffic generated by other devices to the processor, or for which the processor ensures the routing function as master

This time is only spent in the cycles where there is a new message to be managed.

NOTE: These times may not all occur in the same cycle. Messages are sent in the same PLC cycle as instruction execution when communication traffic is low. However, responses are never received in the same cycle as instruction execution.